How to use the include directive in a makefile for a specific target

gnu-make, makefile

I want to use the include directive only for a specific target. I do not want to run the other makefiles when the target is not needed because it means the makefiles are generated needlessly.

So is there a way to conditionally use the include directive, which is conditional on a target? Or somehow to make the include directive a prerequisite of a target.

Here's what I have so far:

# FlagsINCDIR = $(CURDIR)/includeCFLAGS = -Wall -Wno-overflow -Wno-uninitialized -pedantic -std=c99 -I$(INCDIR) -O3LFLAGS = -flat_namespace -dynamiclib -undefined dynamic_lookup# Directory names# Set vpath search pathsvpath %.h includevpath %.c srcvpath %.o buildvpath %.d build# Get files for the core libraryCORE_FILES = $(wildcard src/*.c)CORE_OBJS = $(patsubst src/%.c, build/%.o, $(CORE_FILES))CORE_DEPS = $(CORE_OBJS:.o=.d)# Core library target linkingcore : $(CORE_OBJS) | bin    $(CC) $(LFLAGS) -o bin/libcbitcoin.2.0.dylib $(CORE_OBJS)# Include header prerequisites (How to do only for "core" target?)include $(CORE_DEPS)# Makefiles for header dependencies. $(CORE_DEPS): build/%.d: src/%.c | build    rm -f [email protected]; \    $(CC) -I$(INCDIR) -MM $< -MT '$(@:.d=.o) [email protected]' > [email protected]# Objects depend on directory$(CORE_OBS) : | build# Create build directorybuild:    mkdir build# Create bin directorybin:    mkdir bin# Core Compilation$(CORE_OBJS): build/%.o: src/%.c    $(CC) -c $(CFLAGS) $< -o [email protected]# Depencies require include/CBDependencies.h as a prerequisitebuild/CBOpenSSLCrypto.o: include/CBDependencies.h# Crypto library target linkingcrypto : build/CBOpenSSLCrypto.o -lcrypto -lssl | bin    $(CC) $(LFLAGS) -o bin/libcbitcoin-crypto.2.0.dylib build/CBOpenSSLCrypto.o -lcrypto -lssl# Crypto library compilebuild/CBOpenSSLCrypto.o: dependencies/crypto/CBOpenSSLCrypto.c    $(CC) -c $(CFLAGS) $< -o [email protected]#Cleanclean:    rm -f $(CORE_OBJS) $(CORE_DEPS) build/CBOpenSSLCrypto.o

As you should be able to tell I do not need to include the ".d" files for "crypto" but I do for "core" (default goal).

Thank you for any help.

Best Solution

Make is not a procedural language, so treating it as one goes against the grain; your makefiles will be difficult to scale, and it can lead to subtle bugs.

There's a better way by Tom Tromey that's clean, efficient and scalable. The trick is to realize that you can build the dependency file in the same step as the object file. The dependencies simply tell Make when the object is due to be rebuilt; you don't need them when you first build the object, because Make knows that the object must be built. And if the dependencies change, that can only be because something in the source or the old dependencies has changed, so again Make knows that the object must be rebuilt. (This is not obvious, so it may take a little cogitation.)

$(CORE_OBJS): build/%.o: src/%.c    $(CC) -c $(CFLAGS) $< -o [email protected]    $(CC) -MM -MF build/$*.d $<-include build/*.d

There's one more hitch: if you alter the code so as to remove a dependency -- and also remove that file -- you won't be able to rebuild, because the old dependency list will still demand a file which can no longer be found. The sophisticated solution is to process the dependency file so as to make each prerequisite (e.g. header) a target in its own right, with no commands, so that it can be assumed to be rebuilt when needed:

$(CORE_OBJS): build/%.o: src/%.c    $(CC) -c $(CFLAGS) $< -o [email protected]    $(CC) -MM -MF build/$*.d $<    @cp build/$*.d build/$*.P    @sed -e 's/#.*//' -e 's/^[^:]*: *//' -e 's/ *\\$$//' \            -e '/^$$/ d' -e 's/$$/ :/' < build/$*.P >> build/$*.d;    @rm build/$*.P

A cruder method, but almost as foolproof, is to put in catch-all rules for headers and sources:

$(CORE_OBJS): build/%.o: src/%.c    $(CC) -c $(CFLAGS) $< -o [email protected]    $(CC) -MM -MF build/$*.d $<%.cc %.h:

EDIT:

To break down the new commands:

The -MM option tells gcc to produce a make rule for the object file, instead of preprocessing or compiling. The default is to send the rule to wherever it would send preprocessed output, which will usually be stdout.

The -MF option, used with -MM, specifies the output file. So -MM -MF build/$*.d will put the rule where we want it.

So the following two commands are (almost always) equivalent:

    $(CC) -MM -MF build/$*.d $<    $(CC) -MM $< > build/$*.d

(I've left out the -I$(...) and the possibility of using the -MMD option, because both get a little complicated and are not really the point of the question.)